TPS7301Q datasheet(38/43 Pages) TI

38 / 43 page

TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q

LOW-DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED DELAYED RESET FUNCTION

SLVS124F – JUNE 1995 – REVISED JANUARY 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

Resistors R1 and R2 should be chosen for approximately 7-

µA divider current. A recommended value for R2

is 169 k

Ω with R1 adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherent

advantage and consume more power. Larger values of R1 and R2 should be avoided as leakage currents at

FB will introduce an error. Solving for R1 yields a more useful equation for choosing the appropriate resistance:

ref

* 1

OUTPUT

VOLTAGE

2.5 V

3.3 V

3.6 V

4 V

5 V

6.4 V

UNIT

191

309

348

402

549

750

169

Ω

OUTPUT VOLTAGE

PROGRAMMING GUIDE

RESET

OUT

GND

<0.5 V

>2.7 V

TPS7301

To System

Reset

0.1

µF

250 k

Ω

CSR = 1

Ω

µF

Figure 48. TPS7301 Adjustable LDO Regulator Programming

undervoltage supervisor function

The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event

of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator

to detect the undervoltage condition. When that occurs, the RESET output transistor turns on taking the RESET

signal low.

On power up, the output voltage tracks the input voltage. The RESET output becomes active (low) as VI

approaches the minimum required for a valid RESET signal (specified at 1.5 V for 25

°C and 1.9 V over full

recommended operating temperature range). When the output voltage reaches the appropriate positive-going

input threshold (VIT+), a 200-ms (typical) timeout period begins during which the RESET output remains low.

Once the timeout has expired, the RESET output becomes inactive. Since the RESET output is an open-drain

NMOS, a pullup resistor should be used to ensure that a logic-high signal is indicated.

The supply-voltage-supervisor function is also activated during power-down. As the input voltage decays and

after the dropout voltage is reached, the output voltage tracks linearly with the decaying input voltage. When

the output voltage drops below the specified negative-going input threshold (VIT– — see electrical

characteristics tables), the RESET output becomes active (low). It is important to note that if the input voltage

decays below the minimum required for a valid RESET, the RESET is undefined.

Since the circuit is monitoring the regulator output voltage, the RESET output can also be triggered by disabling

the regulator or by any fault condition that causes the output to drop below VIT–. Examples of fault conditions

include a short circuit on the output and a low input voltage. Once the output voltage is reestablished, either by

reenabling the regulator or removing the fault condition, then the internal timer is initiated, which holds the

RESET signal active during the 200-ms (typical) timeout period.

TPS7301Q Datasheet(PDF) 38 Page - Texas Instruments

TPS7301Q Datasheet(HTML) 38 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

Datasheet Download

Link URL