TSB14C01A, TSB14C01AI, TSB14C01AM

5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER

SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999

15

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

status

When the phy has status information to transfer to the link, it initiates a status transfer. The phy waits until the

interface is idle to perform the transfer. The phy initiates the transfer by asserting status (01) on the CTL

terminals, along with the first two bits of status information on D0 and D1. The phy maintains CTL == status for

the duration of the status transfer. The phy can temporarily halt a status transfer by asserting something other

than status on the CTL terminals. This is done in the event that a packet arrives before the status transfer

completes. There must be at least one idle cycle between consecutive status transfers.

The phy normally sends only the first 4 bits of status to the link. These bits are status flags that are needed by

link state machines. The phy sends an entire status packet to the link after a request transfer that contains a

read request.

The definition of the bits in the status transfer are shown in Table 12 (also see Table 2 and Table 9). The 16-bit

status stream is defined in Table 12.

Table 12. Status Bit Description

Bit(s)

Name

Description

0

Arbitration

Reset gap

Indicates that the phy has detected that the bus has been idle for an

arbitration reset gap time (this time is defined in the 1394 standard). This bit

is used by the link in its busy/retry state machine.

1

Subaction gap

Indicates that the phy has detected that the bus has been idle for a subaction

gap time (this time is defined in the 1394 standard). This bit is used by the

link to detect the completion of an isochronous cycle.

2

Bus reset

Indicates that the phy has entered the bus reset state.

3

Reserved

Reserved

4-7

Address

Holds the address of the phy register whose contents are transferred to the

link.

8-15

Data

Indicates the data that is to be sent to the link.

00

01

01

01

00

00

Phy

CTL0, CTL1

00

S[0,1]

00

00

Phy

D0, D1

S[14,15]

S[2,3]

00

00

Figure 5. Status Transfer Timing