TSB14C01A, TSB14C01AI, TSB14C01AM

5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER

SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999

28

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

bus reset

Once a phy control request of bus reset is communicated from the node controller to the phy, the registers and

CSRs associated with the operation of that phy are initialized to their default values. State machines associated

with phy operations can be initialized. The phy communicates a BUS_RESET onto the bus. After the

BUS_RESET event is detected by the node transmitting it (i.e., approximately 320 arbitration clock times after

the signal is initiated), the phy initializes itself.

NOTE

Since a phy transmitting a BUS_RESET must also react accordingly once the BUS_RESET event

is detected, its state machines do have the opportunity to advance beyond those of other nodes.

This ensures that all nodes are in somewhat similar states after such a bus reset event. Obviously,

the logic (e.g., counters) used within the phy to generate the BUS_RESET signal must not be reset

once that phy simultaneously detects its own BUS_RESET.

Once a phy detects that a BUS_RESET event has occurred on the bus, it initializes itself. The node controller

initiates a bus reset by writing to the phy control register with the IBR bit set to 1. The phy hardware resets the

IBR bit to zero on detection of its own bus reset.

live insertion

It is up to the user to design their node or module to safely receive power from the particular backplane they

are using during a live insertion or tap-in. But in principal, live insertion is supported and does not cause a

bus-reset event to occur. Please see the TI application note,

Live Insertion, TI literature number SDYA012.