TSB41LV02APAP datasheet(39/50 Pages) TI

39 / 50 page

TSB41LV02A

IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MAY 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

transmit (continued)

After sending the last packet for the current bus ownership, the LLC releases the bus by asserting idle on the

CTL terminals for two clock cycles. The PHY begins asserting idle on the CTL terminals one clock after sampling

idle from the link. Note that whenever the D and CTL terminals change direction between the PHY and the LLC,

there is an extra clock period allowed so that both sides of the interface can operate on registered versions of

the interface signals.

(f)

(g)

(e)

(d)

(c)

(b)

(a)

d0, d1, . . .

Link controls CTL and D

PHY High-Impedance CTL and D outputs

D0–D7

CTL0, CTL1

SYSCLK

NOTE A: SPD = Speed code, see Table 20 d0–dn = Packet data

SPD

Figure 20. Normal Packet Transmission Timing

The sequence of events for a normal packet transmission is as follows:1

Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over

control of the interface to the link so that the link may transmit a packet. The PHY releases control of

the interface (i.e., it places its CTL and D outputs in a high-impedance state) following the idle cycle.

Optional idle cycle. The link may assert at most one idle cycle preceding assertion of either hold or

transmit. This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit.

Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of transmit. These

hold cycle(s) are optional; the link is not required to assert hold preceding transmit.

Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along

with the data on the D lines.

Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle

on the CTL lines. The link asserts hold to indicate that the PHY is to retain control of the serial bus in

order to transmit a concatenated packet. The link asserts idle to indicate that packet transmission is

complete and the PHY may release the serial bus. The link then asserts idle for one more cycle following

this cycle of hold or idle before releasing the interface and returning control to the PHY.

Concatenated packet speed-code. If multispeed concatenation is enabled in the PHY, the link asserts

a speed-code on the D lines when it asserts hold to terminate packet transmission. This speed-code

indicates the transmission speed for the concatenated packet that is to follow. The encoding for this

concatenated packet speed-code is the same as the encoding for the received packet speed-code (see

Table 20). The link may not concatenate an S100 packet onto any higher-speed packet.

After regaining control of the interface, the PHY asserts at least one cycle of idle before any subsequent

status transfer, receive operation, or transmit operation.

TSB41LV02APAP Datasheet(PDF) 39 Page - Texas Instruments

TSB41LV02APAP Datasheet(HTML) 39 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Datasheet Download

Link URL