TSB41LV02APAP datasheet(13/50 Pages) TI

13 / 50 page

TSB41LV02A

IEEE 1394a TWO PORT CABLE TRANSCEIVER/ARBITER

SLLS400A – JANUARY 2000 – REVISED MAY 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)

(continued)

thermal characteristics

PARAMETER

TEST CONDITION†

MIN

TYP

MAX

UNIT

θJA

Junction-to-free-air thermal resistance

Board mounted, no air flow, high conductivity TI

recommended test board chip soldered or greased to

25.2

°C/W

θJC Junction-to-case-thermal resistance

recommended test board, chi soldered or greased to

thermal land with 1 oz. copper

1.2

°C/W

θJA

Junction-to-free-air thermal resistance

Board mounted, no air flow, high conductivity TI

recommended test board with thermal land but no solder

56.8

°C/W

θJC Junction-to-case-thermal resistance

or grease thermal connection to thermal land with 1 oz.

copper

1.2

°C/W

θJA

Junction-to-free-air thermal resistance

Board mounted, no air flow, JEDEC test board with 1 oz.

61.6

°C/W

θJC Junction-to-case-thermal resistance

copper

1.2

°C/W

† Use of the thermally-enhanced PowerPAD PAP package is assumed in all three test conditions.

switching characteristics

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

Jitter, transmit

Between TPA and TPB

±0.15

Skew, transmit

Between TPA and TPB

±0.10

TP differential rise time, transmit

10% to 90%,

At 1394 connector

0.5

1.2

TP differential fall time, transmit

90% to 10%,

At 1394 connector

0.5

1.2

tsu

Setup time, CTL0, CTL1, D1–D7, LREQ to SYSCLK

50% to 50%,

See Figure 2

Hold time, CTL0, CTL1, D1–D7, LREQ after SYSCLK

50% to 50%,

See Figure 2

Delay time, SYSCLK to CTL0, CTL1, D1–D7

50% to 50%,

See Figure 3

PARAMETER MEASUREMENT INFORMATION

TPAx+

TPBx+

TPAx–

TPBx–

Ω

Figure 1. Test Load Diagram

tsu

Dx, CTLx, LREQ

SYSCLK

Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms

TSB41LV02APAP Datasheet(PDF) 13 Page - Texas Instruments

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