LPC2919SLASH01 datasheet(23/86 Pages) NXP

23 / 86 page

LPC2917_19_01_2

Preliminary data sheet

Rev. 02 — 17 June 2009

23 of 86

NXP Semiconductors

LPC2917/01; LPC2919/01

ARM9 microcontroller with CAN and LIN

Remark: If the programmed number of wait-states is more than three, ﬂash-data reading

cannot be performed at full speed (i.e. with zero wait-states at the AHB bus) if speculative

reading is active.

6.8.6 EEPROM

EEPROM is a non-volatile memory mostly used for storing relatively small amounts of

data, for example for storing settings. It contains one 16 kB memory block and is

byte-programmable and byte-erasable.

The EEPROM can be accessed only through the ﬂash controller.

6.9 External static memory controller

The LPC2917/2919/01 contains an external Static Memory Controller (SMC) which

provides an interface for external (off-chip) memory devices.

Key features are:

• Supports static memory-mapped devices including RAM, ROM, ﬂash, burst ROM and

external I/O devices.

• Asynchronous page-mode read operation in non-clocked memory subsystems.

• Asynchronous burst-mode read access to burst-mode ROM devices.

• Independent conﬁguration for up to eight banks, each up to 16 MB.

• Programmable bus-turnaround (idle) cycles (one to 16).

• Programmable read and write wait states (up to 32), for static RAM devices.

• Programmable initial and subsequent burst-read wait state for burst-ROM devices.

• Programmable write protection.

• Programmable burst-mode operation.

• Programmable external data width: 8 bits, 16 bits or 32 bits.

• Programmable read-byte lane enable control.

6.9.1 Description

The SMC simultaneously supports up to eight independently conﬁgurable memory banks.

Each memory bank can be 8 bits, 16 bits or 32 bits wide and is capable of supporting

SRAM, ROM, burst-ROM memory, or external I/O devices.

A separate chip select output is available for each bank. The chip select lines are

conﬁgurable to be active HIGH or LOW. Memory-bank selection is controlled by memory

addressing. Table 11 shows how the 32-bit system address is mapped to the external bus

memory base addresses, chip selects, and bank internal addresses.

LPC2919/01 Datasheet(PDF) 23 Page - NXP Semiconductors