LPC2919SLASH01 datasheet(54/86 Pages) NXP

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LPC2917_19_01_2

Preliminary data sheet

Rev. 02 — 17 June 2009

54 of 86

NXP Semiconductors

LPC2917/01; LPC2919/01

ARM9 microcontroller with CAN and LIN

Using the base clocks from the CGU as input, the PMU generates branch clocks to the

rest of the LPC2917/2919/01. Output clocks branched from the same base clock are

phase- and frequency-related. These branch clocks can be individually controlled by

software programming.

The key features are:

• Individual clock control for all LPC2917/2919/01 sub-modules

• Activates sleeping clocks when a wake-up event is detected

• Clocks can be individually disabled by software

• Supports AHB master-disable protocol when AUTO mode is set

• Disables wake-up of enabled clocks when Power-down mode is set

• Activates wake-up of enabled clocks when a wake-up event is received

• Status register is available to indicate if an input base clock can be safely switched off

(i.e. all branch clocks are disabled)

6.15.5.1

Functional description

The PMU controls all internal clocks coming out of the CGU0 for power-mode

management. With some exceptions, each branch clock can be switched on or off

individually under control of software register bits located in its individual conﬁguration

Table 31 shows which mode- control bits are supported by each branch clock.

By programming the conﬁguration register the user can control which clocks are switched

on or off, and which clocks are switched off when entering Power-down mode.

Note that the standby-wait-for-interrupt instructions of the ARM968E-S processor (putting

the ARM CPU into a low-power state) are not supported. Instead putting the ARM CPU

into power-down should be controlled by disabling the branch clock for the CPU.

Remark: For any disabled branch clocks to be re-activated their corresponding base

clocks must be running (controlled by CGU0).

Table 31 shows the relation between branch and base clocks, see also Section 6.7.1.

Every branch clock is related to one particular base clock: it is not possible to switch the

source of a branch clock in the PMU.

Table 31.

Branch clock overview

Legend:

‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored

‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored

‘+’ Indicates that the related register bit is readable and writable

Branch clock name

Base clock

Implemented switch on/off

mechanism

WAKE-UP

AUTO

RUN

CLK_SAFE

BASE_SAFE_CLK

CLK_SYS_CPU

BASE_SYS_CLK

CLK_SYS

BASE_SYS_CLK

CLK_SYS_PCR

BASE_SYS_CLK

CLK_SYS_FMC

BASE_SYS_CLK

LPC2919/01 Datasheet(PDF) 54 Page - NXP Semiconductors

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