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SE97TL Datasheet(PDF) 25 Page - NXP Semiconductors

Part # SE97TL
Description  DDR memory module temp sensor with integrated SPD, 3.3 V
PDF  54 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SE97TL Datasheet(HTML) 25 Page - NXP Semiconductors

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SE97_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 6 August 2009
25 of 54
NXP Semiconductors
SE97
DDR memory module temp sensor with integrated SPD, 3.3 V
8
SHMD
Shutdown Mode.
0 — enabled Temperature Sensor (default)
1 — disabled Temperature Sensor
When shut down, the thermal sensor diode and ADC are disabled to save
power, no events will be generated. When either of the Critical Trip or Alarm
Window lock bits is set, this bit cannot be set until unlocked. However, it can be
cleared at any time.
Remark: SMBus Time-out works over the entire supply range of 1.7 V to 3.6 V
unless the shutdown bit (SHMD) is set and turns off the oscillator.
• The EEPROM read works over the entire supply range of 1.7 V to 3.6 V
whether or not SHMD is set because it does not need oscillator to function.
There is no undervoltage lockout, the device no longer responds at some
voltage below 1.7 V.
• EEPROM write works over the supply range of 3.0 V to 3.6 V, but not if
SHMD is set since the oscillator is needed to write to EEPROM. There is an
undervoltage lockout around 2.7 V that disables the RRPROM write
operation.
• Thermal sensor is operational over the supply range of 3.0 V to 3.6 V, but
not if SHMD is set since the oscillator is needed. There is an undervoltage
lockout around 2.7 V that disables the temp sensor.
Thermal sensor auto turn-off feature:
It was determined during testing of the SE97TP on 5 May 2008 that the Thermal
Sensor auto turn-off feature was not compatible with the JEDEC power supply
maximum ramp rate of 70 ms to 100 ms (slowest ramp rate) and this feature was
disabled for all SE97 samples/production devices tested after 6 May (wk 0818
date code is when the devices were assembled).
If there is a slow ramp rate on the supply voltage to 3.3 V the SE97 would be EE
read only and not Thermal Sensor. This is due to a feature integrated into the
device to automatically turn off the oscillator and place the thermal sensor in
shutdown if the SE97 was being used in SO-DIMM in notebook applications at
1.8 V to reduce the power consumption on the battery. The feature counts for
30 ms (
± 5 ms) after the oscillator starts working (around 1.2 V to 1.7 V) and if at
30 ms the voltage is greater than 2.4 V, the oscillator is left on and the Thermal
Sensor functions as normal. But if the voltage is less than 2.4 V at 30 ms, the
oscillator is turned off and the SE97 will think the part is in SPD only mode
defaulting to the oscillator and Thermal Sensor disabled (SHMD Shutdown
Mode bit 8 = 1). The oscillator and Thermal Sensor can be re-enabled by writing
a logic 0 to SHMD. It is important in RDIMM/server applications that the Thermal
Sensor is working as the default condition since the Thermal Sensor needs to be
compatible with the JEDEC power supply ramp rate (maximum ramp rate is
70 ms to 100 ms) so the Thermal Sensor auto turn-off feature was disabled
starting on 6 May 2008 by changing a programmable bit on the device during
final test. There is no change in performance of the SE97 with this feature turned
off and was verified during characterization. There is no way to read the SE97
registers via the I2C-bus to determine if the Thermal Sensor auto turn-off feature
is enabled or disabled. This is set in a factory only register. You need to check
the date code or do an operational test (e.g., run up to < 2.4 V, hold, then go to
3.3 V, then read SHMD bit 8 in the Configuration register to see if it is set to
logic 0 (e.g., oscillator running = feature disabled) or logic 1 (e.g., oscillator
turned off = feature enabled)). The Thermal Sensor auto turn-off feature is active
in all package options prior to wk 0818. The SE97TP and SE97TL were not yet
released to production so there is a clear line at release/orderable devices
versus samples with this feature disabled in all production devices.
Table 12.
Configuration register (address 01h) bit description …continued
Bit
Symbol
Description



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