SE97TP datasheet(51/54 Pages) NXP

51 / 54 page

SE97_5

Product data sheet

Rev. 05 — 6 August 2009

51 of 54

NXP Semiconductors

SE97

DDR memory module temp sensor with integrated SPD, 3.3 V

15. Revision history

RDIMM

Registered Dual In-line Memory Module

SMBus

System Management Bus

SO-DIMM

Small Outline Dual In-line Memory Module

SPD

Serial Presence Detect

Table 33.

Abbreviations …continued

Acronym

Description

Table 34.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

SE97_5

20090806

Product data sheet

SE97_4

Modiﬁcations:

• Section 1 “General description”, 7th paragraph: deleted 5th sentence

• Section 2.1 “General features”:

– 1st bullet item: changed from “SO-DIMM” to “TSE 2002B3 DIMM

± 0.5 °C (typ.) between 75 °C

and 95

°C”

– 3rd bullet item: changed from “3.0

µA (max.)” to “5.0 µA (max.)”

– 8th bullet item: appended “(JEDEC PSON8 VCED-3)”

• Table 1 “Ordering information”, Table note [2] re-written

• Section 7.3.2.1 “Alarm window”:

– 1st Advisory notiﬁcation, Competitor device: appended “(CEVNT)” to end of phrase

– 1st Advisory notiﬁcation, Work-around: appended “(CEVNT)” to end of phrase

– 2nd Advisory notiﬁcation, Competitor devices: changed from “... when new UPPER or LOWER

and Event bit 3 (EOCTL) are set ... “ to “when new UPPER or LOWER Alarm Windows and the

EVENT output are set ...”

– 2nd Advisory notiﬁcation, Work-around: appended “(EOCTL = 1)” to end of phrase

• Section 7.3.2.2 “Critical trip”

– 1st paragraph, last sentence: changed from “... through the Clear EVENT bit ...”

to “... through the Clear EVENT bit (CEVNT) ...

– Advisory notiﬁcation, Competitor devices: re-written

– Advisory notiﬁcation, Work-around: changed from “Wait at least 125 ms before enabling EVENT

output, Intel will change Nehalem BIOS so that Tth(crit) is set for more than 125 ms before Event

bit 3 (EOCTL) is enabled and Event value is checked.” to “Wait at least 125 ms before enabling

EVENT output (EOCTL = 1), Intel will change Nehalem BIOS so that Tth(crit) is set for more than

125 ms before EVENT output is enabled and Event value is checked.

• Section 7.7 “SMBus time-out”:

– 1st paragraph, 2nd sentence changed from “... holds SCL LOW more than 35 ms” to “... holds

SCL LOW between 25 ns and 35 ns”

– added 2nd “Remark”

• Section 7.8 “SMBus Alert Response Address (ARA)”: added 2nd “Remark”

• Table 12 “Conﬁguration register (address 01h) bit description”, bit 8, SHMD: added “Remark” and

3 bullet items

• Table 29 “DC characteristics”:

– IDD(AV): removed condition “VDD = 3.0 V to 3.6 V”

– IDD(AV): removed sub-row with condition “VDD = 1.7 V”

– Isd(VDD): changed Max value from “3 µA” to “5.0 µA”

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