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TDF8599BTH Datasheet(PDF) 27 Page - NXP Semiconductors |
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TDF8599BTH Datasheet(HTML) 27 Page - NXP Semiconductors |
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27 / 54 page ![]() TDF8599B_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 29 July 2009 27 of 54 NXP Semiconductors TDF8599B I2C-bus controlled dual channel class-D power amplifier 10. Limiting values [1] Floating condition assumed for outputs. [2] Current limiting concept. [3] Human Body Model (HBM). [4] Charged-Device Model (CDM). [5] The output pins are defined as the output pins of the filter connected between the TDF8599B output pins and the load. Table 17. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VP supply voltage Operating mode - 29 V off state [1] −1 +50 V load dump; duration 50 ms; tr > 2.5 ms -50 V IORM repetitive peak output current maximum output current limiting [2] 8- A IOM peak output current maximum; non-repetitive stereo mode - 20 A parallel mode - 13 A Vi input voltage pins SCL, SDA, ADS, MOD, SSM, OSCIO, EN and SEL_MUTE 0 5.5 V pins IN1N, IN1P, IN2N and IN2P 010 V Vo output voltage pins DIAG and CLIP 0 10 V RESR equivalent series resistance as seen between pins VP and PGNDn - 350 m Ω Tj junction temperature - 150 °C Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C VESD electrostatic discharge voltage HBM [3] C = 100 pF; Rs = 1.5 kΩ - 2000 V CDM [4] non-corner pins - 500 V corner pins - 750 V V(prot) protection voltage AC and DC short circuit voltage of output pins across load and to supply and ground [5] 0VP V |
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