LE24LB642CS

Functional Description

1 Start condition

When the SCL line is at the high level, the start condition is established by changing the SDA line from high to low.

The operation of the EEPROM as a slave starts in the start condition.

2 Stop condition

When the SCL line is at the high level, the stop condition is established by changing the SDA line from low to high.

When the device is set up for the read sequence, the read operation is suspended when the stop condition is received,

and the device is set to standby mode. When it is set up for the write sequence, the capture of the write data is ended

when the stop condition is received, and the EEPROM internal write operation is started.

Stop

condition

Start

condition

SCL

SDA

tSU.STA

tHD.STA

tSU.STO

3 Data transfer

Data is transferred by changing the SDA line while the SCL line is low. When the SDA line is changed while the SCL

line is high, the resulting condition will be recognized as the start or stop condition.

SCL

SDA

tSU.DAT

tHD.DAT

4 Acknowledge

During data transfer, 8-bits are transferred in succession, and then in the ninth clock cycle period the device on the

system bus receiving the data sets the SDA line to low, and sends the acknowledge signal indicating that the data has

been received. The acknowledge signal is not sent during an EEPROM internal write operation.

Acknowledge

bit output

Start

condition

SCL

(EEPROM input)

SDA

(Master output)

SDA

(EEPROM output)

1

8

9

tAA

tDH

No.A1464-5/11