LE24LB642CS

5 Device addressing

For the purposes of communication, the master device in the system generates the start condition for the slave device.

Communication with a particular slave device is enabled by sending along the SDA bus the device address, which is

7-bits long, and the read/write command code, which is 1 bit long, immediately following the start condition.

The upper four bits of the device address are called the device code which, for this product, is fixed as “1010.” This

device has the upper 3-bit of the Slave Device address as the Slave address (S0, S1, S2), which fixed on the inside.

The value of Slave address are S0=0, S1=0, S2=0.

When the device code input from SDA and the slave addresses are compared with the product’s device code and slave

addresses that were set at the mounting stage and found to match, the product sends the acknowledge signal during

the ninth clock cycle period, and initiates the read or write operation in accordance with the read or write command

code. If they do not match, the EEPROM returns to standby mode. When a read operation is performed immediately

after the slave device has been switched, the random read command must be used.

No.A1464-6/11

6 EEPROM write operation

6-1. Byte writing

When the EEPROM receives the 7-bit device address and write command code "0" after the start condition, it

generates an acknowledge signal. After this, if it receives 3-bit don’t-care bits and a 13-bit word address, generates an

acknowledge signal, receives the 8-bit writing data, and generates an acknowledge signal when it receives the stop

condition, the rewrite operation of the EEPROM in the designated memory address will start. Rewriting is completed

in the tWC period after the stop condition. During an EEPROM rewrite operation, no input is accepted and no

acknowledge signals are generated.

6-2. Page writing

This product enables pages with up to 32 bytes to be written. The basic data transfer procedure is the same as for byte

writing: Following the start condition, the 9-bit device address and write command code “0,” word address (n), and

data (n) are input in this order while confirming acknowledge “0” every 9 bits. The page write mode is established if,

after data (n) is input, the write data (n+1) is input without inputting the stop condition. After this, the write data

equivalent to the largest page size can be received by a continuous process of repeating the receiving of the 8-bit

write data and generating the acknowledge signals.

At the point when the write data (n+1) has been input, the lower 5 bits (A0-A4) of the word addresses are

automatically incremented to form the (n+1) address. In this way, the write data can be successively input, and the

word address on the page is incremented each time the write data is input. If the write data exceeds 32 bytes or the

last address of the page is exceeded, the word address on the page is rolled over. Write data will be input into the

same address two or more times, but in such cases the write data that was input last will take effect. Finally, the

EEPROM internal write operation corresponding to the page size for which the write data is received starts from the

designated memory address when the stop condition is received.

1

0

1

0

S2

S1

S0

R/W

Device Code

Slave

Address

MSB

LSB

LE24LB642CS

Device address word

SDA

Word Address

0

1

0

S1

1

W

ACK

ACK

ACK

**

*

A

11

A

10

A9 A8

D7 D6 D5 D4 D3 D2 D1 D0

Data

R/W

S2

ACK

A7 A6 A5 A4 A3 A2 A1 A0

S0

A

12

*: don’t care