5

FN6732.0

March 3, 2009

of the interrupt. An unexpected camera flash, for example,

can be ignored by setting the persistency to 8 integration

cycles.

There are eight 8-bit registers available inside the ISL29021.

The two command registers define the operation of the device.

The command registers do not change until the registers are

overwritten. The two 8-bit data Read Only registers are for the

ADC output and the Timer output. The data registers contain

the ADC's latest digital output, or the number of clock cycles in

the previous integration period. The four 8-bit interrupt registers

hold 16-bit interrupt high and low thresholds.

wired as 1000100. When 1000100x with x as R or W is sent

after the Start condition, this device compares the first seven

bits of this byte to its address and matches.

Figure 1 shows a sample one-byte read. Figure 2 shows a

the SCL (clock) line, while either the master or the slave can

drive the SDA (data) line. Figure 2 shows a sample write.

start condition (SDA falling while SCL remains high). The

following byte is driven by the master, and includes the slave

address and read/write bit. The receiving device is

responsible for pulling SDA low during the

the master asserting a stop condition (SDA rising while SCL

remains high).

START

W A

A

A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A

A6 A5 A4 A3 A2 A1 A0 W A

A

A

A D7D6 D5 D4 D3 D2D1 D0

13

5

7

13

57

1 2 3

4 5

6

9

2

4

6

STOP START

SDA DRIVEN BY MASTER

DEVICE ADDRESS

SDA DRIVEN BY ISL29021

DATA BYTE0

REGISTER ADDRESS

OUT

DEVICE ADDRESS

SDA DRIVEN BY MASTER

SDA DRIVEN BY MASTER

24

68 9

2

46

8 9

7

8

13

5

7

8

9

IN

START

W

A

A

A6 A5 A4 A3 A2 A1 A0 W

A R7 R6 R5 R4 R3 R2 R1 R0 A B7 B6 B5 B4 B3 B2 B1 B0

A

A

1

2

615

948

STOP

SDA DRIVEN BY MASTER

FUNCTIONS

REGISTER ADDRESS

DEVICE ADDRESS

SDA DRIVEN BY MASTER

SDA DRIVEN BY MASTER

AA

34

5

7

8

9

2

3

4

6

7

8

1

2

3

5

67

9

A

ISL29021