LT3070EUFD datasheet(12/24 Pages) LINER

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LT3070

3070p

APPLICATIONS INFORMATION

component cost savings. The LT3070 steps to the next

level of performance for the latest generation FPGAs, DSPs

and microprocessors. The simple versatility and beneﬁts

derived from these circuits exceed the power supply needs

of today’s high performance microprocessors.

Programming Output Voltage

Three tri-level input pins, VO2, VO1 and VO0, select the

value of output voltage. Table 1 illustrates the 3-bit digital

word to output voltage table resulting from setting these

pins high, low or allowing them to ﬂoat.

These pins may be tied high or tied low by either pin-strap-

ping them to VBIAS or driving them with digital ports. Pins

that ﬂoat may either actually ﬂoat or require logic that has

Hi-Z output capability. This allows output voltage to be

dynamically changed if necessary.

Output voltage is selectable from a minimum of 0.8V to

a maximum of 1.8V in increments of 50mV. The MSB,

VO2, sets the pedestal voltage, and the LSB’s, VO1 and

VO0 increment VOUT.

Output voltage is limited to 1.8V maximum by an internal

override of VO1 (default to “0”) when VO2 = “1”.

Table 1: VO2-VO0 Settings vs Output Voltage

VO2

VO1

VO0

VOUT(NOM)

VO2

VO1

VO0

VOUT(NOM)

0.80V

1.35V

0.85V

1.40V

0.90V

1.45V

0.95V

1.50V

1.00V

1.55V

1.05V

1.60V

1.10V

1.65V

1.15V

1.70V

1.20V

1.75V

1.25V

1.80V

1.30V

X = Don’t Care, 0 = GND, Z = Float, 1 = VBIAS

The input logic “0” threshold is less than 220mV referenced

to GND and the logic “1” threshold is greater than VBIAS

– 500mV. The range between these two thresholds deﬁnes

the logic Hi-Z state.

REF/BYP—Voltage Reference

This pin is the buffered output of the internal bandgap

reference and has an output impedance of

≅19kΩ. The

design includes an internal compensation pole at fC = 4kHz.

A 10nF REF/BYP capacitor to GND creates a lowpass pole

at fLP = 840Hz. The 10nF capacitor decreases reference

voltage noise to about 10μVRMS and soft-starts the refer-

ence. The LT3070 only soft-starts the reference voltage

during an initial turn-on sequence. If the EN pin is toggled

low after initial turn-on, the reference remains powered-up.

Therefore, toggling the EN pin from low to high does not

soft-start the reference. Only by turning the BIAS supply

voltage on and off will the reference be soft-started. Output

voltage noise is the RMS sum of the reference voltage

noise in addition to the ampliﬁer noise.

The REF/BYP pin must not be DC loaded by anything except

for applications that parallel other LT3070 regulators for

higher output currents. Consult the Applications Section

on Paralleling for further details.

Output Voltage Margining

Two tri-level input pins, MARGSEL (polarity) and MARGTOL

(scale), select the polarity and amount of output voltage

margining. Margining is programmable in increments of

±1%, ±3% and ±5%. Margining is internally implemented

as a scaling of the reference voltage.

Table 2 illustrates the 2-bit digital word to output voltage

margining resulting from setting these pins high, low or

allowing them to ﬂoat.

These pins may be set high or set low by either pin-strap-

ping them to VBIAS or driving them with digital ports. Pins

that ﬂoat may either actually ﬂoat or require logic that has

“Hi-Z” output capability. This allows output voltage to be

dynamically margined if necessary.

The MARGSEL pin determines both the polarity and the

active state of the margining function. The logic “low”

threshold is less than 220mV referenced to GND and

enables negative voltage margining. The logic “high”

threshold is greater than VBIAS – 500mV and enables

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