PRODUCT SPECIFICATION

TMC3503

REV. 1.02 11/24/99

9

Application Notes

Figure 4 illustrates a typical TMC3503 interface circuit. In

this example, an optional 1.2 Volt bandgap reference is con-

reference source.

Grounding

It is important that the TMC3503 power supply is well-regu-

lated and free of high-frequency noise. Careful power supply

decoupling will ensure the highest quality video signals at

the output of the circuit. The TMC3503 has separate analog

and digital circuits. To keep digital system noise from the

D/A converter, it is recommended that power supply voltages

ground connections (GND) be made to the analog ground

plane. Power supply pins should be individually decoupled

at the pin.

Printed Circuit Board Layout

Designing with high-performance mixed-signal circuits

demands printed circuits with ground planes. Overall system

performance is strongly influenced by the board layout.

Capacitive coupling from digital to analog circuits may

result in poor D/A conversion. Consider the following sug-

gestions when doing the layout:

1.

possible from all digital signals. The TMC3503 should

be located near the board edge, close to the analog out-

put connectors.

2.

The power plane for the TMC3503 should be separate

from that which supplies the digital circuitry. A single

the power supply for the TMC3503 is the same as that of

the system's digital circuitry, power to the TMC3503

should be decoupled with 0.1µF and 0.01µF capacitors

and isolated with a ferrite bead.

3.

The ground plane should be solid, not cross-hatched.

Connections to the ground plane should have very short

leads.

4.

If the digital power supply has a dedicated power plane

layer, it should not be placed under the TMC3503, the

voltage reference, or the analog outputs. Capacitive cou-

pling of digital power supply noise from this layer to the

TMC3503 and its related analog circuitry can have an

adverse effect on performance.

5.

CLK should be handled carefully. Jitter and noise on

this clock will degrade performance. Terminate the

clock line carefully to eliminate overshoot and ringing.

Figure 4. Typical Interface Circuit

65-3503-05

R7-0

G7-0

B7-0

+5V

0.1

µF

10

µF

VDD

GND

TMC3503

Triple 8-bit

D/A Converter

CLK

SYNC

BLANK

RED PIXEL

INPUT

GREEN PIXEL

INPUT

BLUE PIXEL

INPUT

CLOCK

SYNC

BLANK

COMP

VREF

RREF

WHITE

WHITE

SLEEP

SLEEP

+5V

0.1

µF

0.1

µF

590

Ω

3.3k

Ω

LM185-1.2

(Optional)

IOR

IOS

IOG

IOB

75

Ω

75

Ω

75

Ω

75

Ω

75

Ω

75

Ω

ZO=75Ω

ZO=75Ω

ZO=75Ω

Red

Green w/Sync

Blue