CSF8037b

Rev. 2

11/20/96

10/100 LAN Interface Module with

Enhanced Common Mode Attenuation

The circuit below is a guideline for interconnecting PCA’s EPF8037 with National DP83840A and DP83223 twister chip set

for 10/100 Mb/s applications. Further details can be obtained from the chip manufacturer application notes. Please

consult PCA for applications help regarding the SSI78Q2120 or ICS1890 series parts or consult with the respective

application notes.

Typical insertion loss of the isolation transformer is 0.5dB. This parameter covers the entire spectrum of the encoded

signals in 10/100 protocols. Under terminated conditions, to transmit a 2V pk-pk signal across the cable, you must adjust

the TXREF resistor of the twister chip to get at least 2.12V pk-pk across pins 16-15.

Note that significant low frequency response improvement can be obtained in the system (improving equalization effects) if

the DC blocking capacitors were not used; this can only be done by choosing a different pinout for the 10 Base-T receiver

side. This is accomplished without impacting any other behavior. If any user has a need to improve this feature, please

consult with the PCA Technical support group . This solution is similar to approaches used in EPF8013GM, EPF8022G and

EPF8038S (a repeater interface module).

It is recommended that system designers do not ground the receiver side center tap, via a capacitor. This may worsen

EMI, specifically if the secondary “common mode termination” is pulled to chassis ground as shown.

The phantom resistors shown around the connector have been known to suppress unwanted radiation that unused wires

pick up from the immediate environment. Their placement and use are to be considered carefully before a design is

finalized.

The “common mode termination” load of 75

Ω shown from the center taps of the secondary may be taken to chassis ground

via a cap of suitable value. This depends upon user’s design, EMI margin etc.

It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit

the plane off at least 0.05 inches away from the chip side pins of EPF8037. There need not be any ground plane beyond

this point.

For best results, PCB designer should design the outgoing traces preferably to be 50

Ω, balanced and well coupled to

achieve minimum radiation from these traces.

Typical Application Circuit for UTP (Excerpts from NSC DP83840A application notes)

DP83223

DP83840A

RXD

TXU

TD

RD

SD

RXI

TXO

PMRD

SD

PMID

EPF8037

+

-

+

-

+

-

+

-

+

-

0.10

µF {Note 1}

0.1

µF

{Note 1}

1000pF

1000pF

Other pull down/up resistors not shown, for clarification please refer to National’s application notes.

12.1

Ω

12.1

Ω

9

8

7

11

13

12

1

2

4

5

6

Notes : 1. See text above for clarification.

2. Only Hub side connections are shown.

E L E C T R O N I C S I N C .

RJ45*

8

7

5

4

2

3

6

Chassis

Ground

2000V

50

Ω

50

Ω

75

Ω

75

Ω

Isolation Cap

Rcv

Xmit

1

TEL: (818) 892-0761

FAX: (818) 894-5791

http://www.pca.com

PCA ELECTRONICS, INC.

16799 SCHOENBORN ST.

NORTH HILLS, CA 91343