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CS48560 Datasheet(PDF) 17 Page - Cirrus Logic |
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CS48560 Datasheet(HTML) 17 Page - Cirrus Logic |
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17 / 26 page ![]() CS485xx Family Data Sheet 32-bit Audio Decoder DSP Family DS734F3 Copyright 2009 Cirrus Logic, Inc. 17 CONFIDENTIAL Figure 6. Serial Control Port - I2C Master Mode Timing 5.13 Switching Characteristics — Digital Audio Slave Input Port Figure 7. Digital Audio Input (DAI) Port Timing Diagram 5.14 Switching Characteristics — DSD Slave Input Port Parameter Symbol Min Max Unit DAI_SCLK period Tdaiclkp 40 - ns DAI_SCLK duty cycle - 45 55 % Setup time DAI_DATAn tdaidsu 10 - ns Hold time DAI_DATAn tdaidh 5- ns Parameter Symbol Min Typ Max Unit DSD_SCLK Pulse Width Low tsclkl 78 - - ns DSD_SCLK Pulse Width High tsclkh 78 - - ns DSD_SCLK Frequency (64x Oversampled) - 1.024 - 3.2 MHz DSD_A / _B valid to DSD_SCLK rising setup time tsdlrs 20 - - ns DSD_SCLK rising to DSD_A or DSD_B hold time tsdh 20 - - ns SCP_CLK SCP_SDA 0 1 67 80 1 7 tiicckl tiicckh tiicsu tiich A6 A0 R/W ACK LSB 8 ACK MSB tiicstp 6 tiicdov tiicbf tiicstscl tiicckcmd fiicck tiicckcmd tiicf tiicr DAI_SCLK DAI_DATAn tdaidh tdaidsu |
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