CS485xx Family Data Sheet

32-bit Audio Decoder DSP Family

18

Copyright 2009 Cirrus Logic, Inc.

DS734F3

CONFIDENTIAL

Figure 8. Direct Stream Digital - Serial Audio Input Timing

5.15 Switching Characteristics — Digital Audio Output Port

Parameter

Symbol

Min

Max

Unit

DAO_MCLK period

40

-

ns

DAO_MCLK duty cycle

-

45

55

%

1. Master mode timing specifications are characterized, not production tested.

40

-

ns

-40

60

%

2. Master mode is defined as the CS48DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce

DAO_SCLK, DAO_LRCLK.

DAO_SCLK delay from DAO_MCLK rising edge,

DAO_MCLK as an input

-19

ns

3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the

data is valid.

-8

ns

-8

ns

DAO1_DATA[3..0], DAO2_DATA[1..0]

-10

ns

4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

DAO1_DATA[3..0], DAO2_DATA[1..0]

-15

ns

-30

ns

-15

ns