MPC235 datasheet(13/50 Pages) MEGAWIN

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MPC235 Data Sheet

Watchdog Timer (WDT)

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00DEH

WDT_ST

RSTS

WDT 3WDT 2WDT 1

WDT 0

√

00DFH

WDT_CLR

CLR

√

WDT［3:0］ : Contents of WDT

RSTS: WDT reset status, set by hardware when WDT overflows, clear by firmware or hardware

reset

CLR: RSTS clear and WDT reset control bit, program can clear RSTS and reset WDT by writing

“1” into this bit

The watchdog timer (WDT) is organized as a 4-bit counter designed to prevent the program from

unknown errors.

If the WDT overflows, the WDT reset function will be performed.

RSTS (Bit 7

of WDT_ST) is set by hardware when the WDT overflows and is cleared by hardware reset or

writing 1 to bit 7 of WDT_CLR.

The interval of WDT to cause reset is about 0.7s at 6MHz

external oscillator.

Programming one into the bit 7 of WDT_CLR register can reset the contents

of the WDT.

In normal operation, the application program must reset WDT before it overflows. A

WDT overflow indicates that operation is not under control and the chip will be reset. The

organization of the watchdog timer is shown as below

Overflow signal

WDT

Qw1

Qw2

Qw4

Qw3

System Reset

Hardware reset

WDT_CLR.7 <- 8XH

WDT_ST.7

Fosc/2^18

MPC235 Datasheet(PDF) 13 Page - Megawin Technology Co., Ltd

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