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13

HMC680LP4 / 680LP4E

v03.0609

BiCMOS MMIC 5-BIT DIGITAL

VARIABLE GAIN AMPLIFIER, 30 - 400 MHz

Absolute Maximum Ratings

RF Input Power

20 dBm

RF Output Power

22 dBm

Digital Inputs (B0-B4, Latch Enable)

-0.5 to Vdd +0.5V

Bias Voltage (Vdd)

5.6 V

Channel Temperature

125 °C

Continuous Pdiss (T = 85 °C)

(derate 42 mW/°C above 85 °C)

1.7 W

Thermal Resistance

(channel to ground paddle)

24 °C/W

Storage Temperature

-65 to +150 °C

Operating Temperature

-40 to +85 °C

ELECTROSTATIC SENSITIVE DEVICE

OBSERVE HANDLING PRECAUTIONS

Amp Bias Voltage

Idd (Typ.) (mA)

5V

244

ATTENUATION (dB)

B2

B1

B0

0

0

0000

1

0

0001

2

0

0010

3

0

0011

4

0

0100

5

0

0101

6

0

0110

7

0

0111

8

0

1000

9

0

1001

10

01010

11

01011

12

01100

13

01101

14

01110

15

01111

16

1

X

000

17

1

X

001

18

1

X

010

19

1

X

011

20

1

X

100

21

1

X

101

22

1

X

110

23

1

X

111

[1] Enabling B4 disables B3, the minimum attenuation is 16 dB

Truth Table

Harmonics vs. Frequency

Supply Current vs. Temperature

-100

-80

-60

-40

-20

0

0

0.1

0.2

0.3

0.4

0.5

0.6

2nd Harmonic

3rd Harmonic

FREQUENCY (GHz)

200

220

240

260

280

4.5

5

5.5

-40C

+25C

+85C

VOLTAGE (V)

Control Interface:

The gain of HMC680LP4(E) is controlled by adjusting the state of the attenuator. The attenuator has a 5-bit parallel

CMOS/TTL compatible interface. State of the attenuator can be set with respect to the truth table above.

Power on sequence:

The ideal power up sequence is: GND, Vdd, Digital inputs, RF inputs. Relative order of the digital inputs is not

important as long as they are powered after VDD/GND.

Control Voltage Table

State

Vdd = +3V

Vdd = +5V

Low

0 to 0.5V @ <1 μA

0 to 0.8V @ <1 μA

High

2 to 3V @ <1 μA

2 to 5V @ <1 μA