STM8L101F2P3ATR datasheet(60/77 Pages) STMICROELECTRONICS

60 / 77 page

Electrical parameters

STM8L101xx

60/77

Doc ID 15275 Rev 7

Figure 36.

Typical application with I2C bus and timing diagram 1)

1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD

9.3.8

Comparator characteristics

REPEATED START

START

STOP

START

tf(SDA)

tr(SDA)

tsu(SDA)

th(SDA)

tf(SCK)

tr(SCK)

tw(SCKL)

tw(SCKH)

th(STA)

tsu(STO)

tsu(STA)

tw(STO:STA)

SDA

SCL

4.7k

SDA

STM8L

SCL

VDD

100

VDD

4.7k

I2CBUS

Table 33.

Comparator characteristics

Symbol

Parameter

Conditions

Min (1)

Typ

Max(1)

Unit

VIN(COMP_REF)

Comparator external reference

-0.1

VDD-1.25

VIN

Comparator input voltage range

-0.25

VDD+0.25

Voffset

(2)

Comparator offset error

±20

tSTART

Startup time (after BIAS_EN)

3(1)

µs

IDD(COMP)

Analog comparator consumption

25(1)

µA

Analog comparator consumption

during power-down

60(1)

tpropag

(2)

Comparator propagation delay

100 mV input step

with 5 mV overdrive,

input rise time = 1 ns

2(1)

µs

Data guaranteed by design, not tested in production.

The comparator accuracy depends on the environment. In particular, the following cases may reduce the accuracy of the

comparator and must be avoided:

– Negative injection current on the I/Os close to the comparator inputs

– Switching on I/Os close to the comparator inputs

– Negative injection current on not used comparator input.

– Switching with a high dV/dt on not used comparator input.

These phenomena are even more critical when a big external serial resistor is added on the inputs.

STM8L101F2P3ATR Datasheet(PDF) 60 Page - STMicroelectronics

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