STM8L101F2P3ATR datasheet(63/77 Pages) STMICROELECTRONICS

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STM8L101xx

Electrical parameters

Doc ID 15275 Rev 7

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Static latch-up

●

LU: 2 complementary static tests are required on 10 parts to assess the latch-up

performance. A supply overvoltage (applied to each power supply pin) and a current

injection (applied to each input, output and configurable I/O pin) are performed on each

sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,

refer to the application note AN1181.

9.4

Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in

Table 16: General operating conditions on page 40.

The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated

using the following equation:

TJmax = TAmax + (PDmax x ΘJA)

Where:

●

TAmax is the maximum ambient temperature in ° C

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ΘJA is the package junction-to-ambient thermal resistance in ° C/W

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PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)

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PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip

internal power.

●

PI/Omax represents the maximum power dissipation on output pins

Where:

PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*IOH),

taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in

the application.

Table 37.

Electrical sensitivities

Symbol

Parameter

Class

Static latch-up class

STM8L101F2P3ATR Datasheet(PDF) 63 Page - STMicroelectronics