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PA92 Datasheet(PDF) 3 Page - Cirrus Logic |
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PA92 Datasheet(HTML) 3 Page - Cirrus Logic |
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3 / 6 page ![]() P r o d u c t I n n o v a t i o n F r o m PA92 PA92U 3 NOTES: 1. (AllMin/MaxcharacteristicsandspecificationsareguaranteedovertheSpecifiedOperatingCondi- tions.Typicalperformancecharacteristicsandspecificationsarederivedfrommeasurementstaken attypicalsupplyvoltagesandT C=25°C). 2. Longtermoperationatthemaximumjunctiontemperaturewillresultinreducedproductlife.Derate powerdissipationtoachievehighMTTF. 3. +V Sand–VSdenotethepositiveandnegativepowersupplyrailrespectively. 4. Ratingappliesiftheoutputcurrentalternatesbetweenbothoutputtransistorsataratefasterthan 60Hz. 5. Deratemaxsupplyrating0.625V/°Cbelow25°Ccase.Noderatingneededabove25°Ccase. Parameter Test Conditions Min Typ Max Units CAPACITIVELOAD,A V = +1 Fulltemperaturerange 1 nF SETTLINGTIMEto0.1% C C=10pF,2Vstep 1 µS RESISTANCE,noload 10 Ω POWER SUPPLY VOLTAGE(Note5) ±50 ±150 ±200 V CURRENT, quiescent 10 14 mA THERMAL RESISTANCE,AC,junctiontocase (Note 4) Fulltemprange,F>60Hz 1 °C/W RESISTANCE,DC,junctiontocase Fulltemprange,F<60Hz 1.5 °C/W RESISTANCE,junctiontoair Fulltemprange 30 °C/W TEMPERATURERANGE,case Meetsfullrangespecifications -25 +85 °C 1 2 3 4 5 6 7 8 9 10 –IN +IN RCL +Vs –Vs TO LOAD AND FEEDBACK 11 12 Rc Cc * * (See text.) * Bypassing required. IQ PATENTED 12-pin SIP PACKAGE STYLE DP Formedleadsavailable SeepackagestyleEE ExTERNAL CONNECTIONS PHASE COMPENSATION GAIN C C* R C ≥1 150pF 100Ω ≥2 100pF 100Ω ≥3 47pF 0Ω ≥12 10pF 0Ω *C CNevertobe<10pF.CCtoberatedforthefullsupplyvoltage+Vto-Vs.UseceramicNPO(COG)type. |
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