MCP3909 datasheet(6/44 Pages) MICROCHIP

6 / 44 page

MCP3909

DS22025B-page 6

TIMING CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V to 5.5V,

AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.

Parameter

Sym

Min

Typ

Max

Units

Comment

Frequency Outputs

FOUT0 and FOUT1 Pulse Width

(Logic Low)

tFW

—

275

—

984376 MCLK periods

(Note 1)

HFOUT Pulse Width

tHW

—

322160 MCLK periods

(Note 2)

FOUT0 and FOUT1 Pulse Period

tFP

Refer to Equation 4-1

HFOUT Pulse Period

tHP

Refer to Equation 4-2

FOUT0 to FOUT1 Falling-Edge

Time

tFS2

—

0.5 tFP

—

FOUT0 to FOUT1 Minimum Sepa-

ration

tFS

—

4/MCLK

—

Digital I/O

FOUT0 and FOUT1 Output High

Voltage

VOH

4.5

——

VIOH = 10 mA, DVDD = 5.0V

FOUT0 and FOUT1 Output Low

Voltage

VOL

——

0.5

IOL = 10 mA, DVDD = 5.0V

HFOUT and NEG Output High

Voltage

VOH

4.0

——

VIOH = 5 mA, DVDD = 5.0V

HFOUT and NEG Output Low

Voltage

VOL

——

0.5

IOL = 5 mA, DVDD = 5.0V

High-Level Input Voltage

(All Digital Input Pins)

VIH

2.4

——

VDVDD = 5.0V

Low Level Input Voltage

(All Digital Input Pins)

VIL

——

0.85

DVDD = 5.0V

Input Leakage Current

—0.1

±1

µA

VIN = 0, VIN = DVDD

Pin Capacitance

——

(Note 3)

Serial Interface Timings (Note 4)

Data Ready Pulse Width

tDR

4/MCLK

Reset Time

tRST

100

—

Output Data Rate

fADC

—MCLK/256

—

Serial Clock Frequency

fCLK

—20

MHz

VDD = 5V

Window for serial mode entry

codes

tWINDOW

——

32/

MCLK

—

Last bit must be clocked in

before this time.

Window start time for serial

mode entry codes

tWINSET 1/MCLK

—

First bit must be clocked in

after this time.

Serial Clock High Time

tHI

—

fCLK= 20 MHz

Serial Clock Low Time

tLO

—

fCLK= 20 MHz

CS Fall to First Rising CLK Edge

tSUCS

—

Data Input Setup Time

tSU

—

Data Input Hold Time

tHD

—

Note 1: If output pulse period (tFP) falls below 984376*2 MCLK periods, then tFW = 1/2 tFP.

2: If output pulse period (tHP) falls below 322160*2 MCLK periods, then tHW = 1/2 tHP. When F2, F1, F0

equals 0,1,1, the HFOUT pulse time is fixed at 64 x MCLK periods or 18 µs for MCLK = 3.58 MHz

3: Specified by characterization, not production tested.

4: Serial timings specified and production tested with 180 pF load.

MCP3909 Datasheet(PDF) 6 Page - Microchip Technology

MCP3909 Datasheet(HTML) 6 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Datasheet Download

Link URL