MCP4131 datasheet(43/88 Pages) MICROCHIP

43 / 88 page

DS22060B-page 43

MCP413X/415X/423X/425X

6.1.4

SERIAL CLOCK (SCK)

(SPI FREQUENCY OF OPERATION)

The SPI interface is specified to operate up to 10 MHz.

The actual clock rate depends on the configuration of

the system and the serial command used. Table 6-1

shows the SCK frequency for different configurations.

TABLE 6-1:

SCK FREQUENCY

6.1.5

THE CS SIGNAL

The Chip Select (CS) signal is used to select the device

and frame a command sequence. To start a command,

or sequence of commands, the CS signal must

transition from the inactive state (VIH) to an active state

(VIL or VIHH).

After the CS signal has gone active, the SDO pin is

driven and the clock bit counter is reset.

If an error condition occurs for an SPI command, then

the Command byte’s Command Error (CMDERR) bit

(on the SDO pin) will be driven low (VIL). To exit the

error condition, the user must take the CS pin to the VIH

level.

When the CS pin returns to the inactive state (VIH) the

SPI module resets (including the address pointer).

While the CS pin is in the inactive state (VIH), the serial

interface is ignored. This allows the Host Controller to

interface to other SPI devices using the same SDI,

SDO, and SCK signals.

The CS pin has an internal pull-up resistor. The resistor

is disabled when the voltage on the CS pin is at the VIL

level. This means that when the CS pin is not driven,

the internal pull-up resistor will pull this signal to the VIH

level.

When the CS pin is driven low (VIL), the

resistance becomes very large to reduce the device

current consumption.

The high voltage capability of the CS pin allows

MCP413X/415X/423X/425X devices to be used in

systems previously designed for the MCP414X/416X/

424X/426X devices.

Memory Type Access

Command

Read

Write,

Increment,

Decrement

Volatile

Memory

SDI, SDO

10 MHz

SDI/SDO(1) 250 kHz (2)

10 MHz

Note 1: MCP41X1 devices only.

2: This is the maximum clock frequency

without an external pull-up resistor.

Note:

There is a required delay after the CS pin

goes active to the 1st edge of the SCK pin.

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