MCP23018-ESLASHSS datasheet(23/56 Pages) MICROCHIP

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DS22103A-page 23

MCP23018/MCP23S18

1.6.6

CONFIGURATION REGISTER

The

IOCON

contains

several

bits

for

configuring the device:

The BANK bit changes how the registers are mapped

(see Table 1-4 and Table 1-5 for more details).

• If BANK = 1, the registers associated with each

port are segregated. Registers associated with

PORTA are are mapped from address 00h - 0Ah

and registers associated with PORTB are

mapped from Address 10h - 1Ah

• If BANK = 0, the A/B registers are paired. For

example, IODIRA is mapped to address 00h and

IODIRB is mapped to the next address (address

01h). The mapping for all registers is from 00h -

15h

It is important to take care when changing the BANK bit

as the address mapping changes after the byte is

clocked into the device. The address pointer may point

to an invalid location after the bit is modified.

For example, if the device is configured to automati-

cally increment its internal address pointer the following

scenario would occur:

• BANK = 0

• Write 80h to 0Ah (IOCON) to set the BANK bit

• After the write completes the internal address now

points to 0Bh which is an invalid address when

the BANK bit is set

For this reason, it is advised to only perform byte writes

to this register when changing the BANK bit.

The MIRROR bit controls how the INTA and INTB pins

function with respect to each other.

• When MIRROR = 1, the INTn pins are functionally

OR’ed so that an interrupt on either port will cause

both pins to activate

• When MIRROR = 0, the INT pins are separated.

Interrupt conditions on a port will cause its respec-

tive INT pin to activate

The Sequential Operation (SEQOP) controls the

incrementing function of the address pointer. If the

address pointer is disabled, the address pointer does

not automatically increment after each byte is clocked

during a serial transfer. This feature is useful when it is

desired to continuously poll (read) or modify (write) a

The Open-Drain (ODR) control bit enables/disables the

INT pin for open-drain configuration.

The Interrupt Polarity (INTPOL) sets the polarity of the

INT pin. This bit is functional only when the ODR bit is

cleared, configuring the INT pin as active push-pull.

The Interrupt Clearing Control (INTCC) configures how

interrupts are cleared. When set (INTCC = 1), the

interrupt is cleared when the INTCAP register is read.

When cleared (INTCC = 0), the interrupt is cleared

when the GPIO register is read.

The interrupt can only be cleared when the interrupt

condition is inactive. Refer to Section 1.7.5 “Clearing

Interrupts” for details.

Note:

The INTB pin is not bonded out on the

MCP23S18 (SPI) device in the 24-lead

QFN package. The MIRROR bit must be

configured to a “1” in order for interrupts to

be detected on PORTB.

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