PCF2119DUSLASH2SLASH2 datasheet(49/79 Pages) NXP

49 / 79 page

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

49 of 79

NXP Semiconductors

PCF2119x

LCD controllers/drivers

15. Dynamic characteristics

Table 36.

Dynamic characteristics

VDD1 = 1.5 V to 5.5 V; VDD2 =VDD3 = 2.2 V to 4.0 V; VSS =0V; VLCD = 2.2 V to 6.5 V; Tamb = −40 °C to +85 °C; unless

otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Clock and oscillator

ffr(LCD)

LCD frame frequency

internal clock; VDD = 5.0 V

147

fosc

oscillator frequency

not available at any pin

140

250

450

kHz

fosc(ext)

external oscillator frequency

140

450

kHz

td(startup)(OSC)

start-up delay time on pin OSC

oscillator, after power-down

[1] -

200

300

µs

Timing characteristics of parallel interface[2]

Write operation (writing data from microcontroller to PCF2119x); see Figure 34

tcy(en)

enable cycle time

500

tw(en)

enable pulse width

220

tsu(A)

address set-up time

th(A)

address hold time

tsu(D)

data input set-up time

th(D)

data input hold time

Read operation (reading data from PCF2119x to microcontroller); see Figure 35

tcy(en)

enable cycle time

500

tw(en)

enable pulse width

220

tsu(A)

address set-up time

th(A)

address hold time

td(DV)

data input valid delay time

VDD1 > 2.2 V

150

VDD1 > 1.5 V

250

th(D)

data input hold time

100

Timing characteristics of I2C-bus interface[2]; see Figure 36

fSCL

SCL clock frequency

400

kHz

tLOW

LOW period of the SCL clock

1.3

µs

tHIGH

HIGH period of the SCL clock

0.6

µs

tSU;DAT

data set-up time

100

tHD;DAT

data hold time

rise time of both SDA and SCL

signals

[1][3] 15 + 0.1 Cb -

300

fall time of both SDA and SCL

signals

[1][3] 15 + 0.1 Cb -

300

capacitive load for each bus

line

400

tSU;STA

set-up time for a repeated

START condition

0.6

µs

tHD;STA

hold time (repeated) START

condition

0.6

µs

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