MPC5643L datasheet(70/98 Pages) FREESCALE

70 / 98 page

MPC5643L Microcontroller Data Sheet, Rev. 3

Preliminary—Subject to Change Without Notice

Electrical characteristics

Freescale Semiconductor

tlpll

D PLL lock time 6, 7

—

200

μs

tdc

D Duty cycle of reference

—40

—

CJITTER

CLKOUT period jitter8,9,10,11

Peak-to-peak (clock edge to clock

edge), fSYS maximum

TBD

—

TBD

fCLK

OUT

Long-term jitter (avg. over 2 ms

interval), fSYS maximum

–6

—

Δt

PKJIT

Single period jitter (peak to peak) PHI @ 16 MHz,

Input clock @ 4 MHz

——

±500

Δt

LTJIT

Long term jitter

PHI @ 16 MHz,

Input clock @ 4 MHz

——

±6

fLCK

Frequency LOCK range

—–6

—

fsys

fUL

Frequency un-LOCK range

—–18

—

fsys

fCS

fDS

Modulation Depth

Center spread

±0.25

—

±4.012

fsys

Down Spread

–0.5

—

-8.0

fMOD

D Modulation frequency13

—

100

kHz

NOTES:

1 Considering operation with PLL not bypassed.

2 With FM, +2% maximum.

3 “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked

mode.

4 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside

the fLOR window.

5 f

VCO self clock range is 20-150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in

enhanced mode.

6 This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for

this PLL, load capacitors should not exceed these limits.

7 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits

in the synthesizer control register (SYNCR).

8 This value is determined by the crystal manufacturer and board design.

9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum

fSYS. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock

signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency

increase the CJITTER percentage for a given interval.

10 Proper PC board layout procedures must be followed to achieve specifications.

11 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C

JITTER and

either fCS or fDS (depending on whether center spread or down spread modulation is enabled).

12 This value is true when operating at frequencies above 60 MHz, otherwise f

CS is 2% (above 64 MHz).

13 Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50kHz.

Table 19. FMPLL electrical characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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