NJU6010

Ver.2009-08-20

- 2 -

Preliminary

!

TERMINAL DESCRIPTION

No.

SYMBOL

FUNCTION

1

TEST

Oscillation Circuit Test Terminal

2

CSb

Data output is available by "L".

3

SCL

Serial Clock Input Terminal

4

DATA

Serial Data Output Terminal (This terminal outputs both the serial data

and REQ signals.)

CSb=”H” : Request signal output, CSb=”L” : Key data output

5 ~ 8

S0 ~ S3

Key Scanning Output Terminals

9

VSS

GND Terminal

10 ~ 15

K0 ~ K5

Key Scanning Input Terminals

16

VDD

Power Source Terminal

! FUNCTIONAL DESCRIPTION

(1) Description for Each Blocks

•

Serial I/F

The Serial I/F operates control of output signal.

•

Power ON Reset Circuit

The Power ON Reset Circuit initializes the key register automatically at Power ON.

•

Key-scan Circuit

When the key pressed, the Key-scan Circuit output the request signal from DATA terminal. The key data is

kept in the key register until CPU starts reading key data.

•

Key Register

The Key Register keeps the read key data.

•

Oscillation Circuit

The oscillation circuit is built-in.

(2) Key-scan Circuit

The Key-scan Circuit consists of a detector block of key pressing (S0~S3) and a fetching block of key

status (K0~K5). The Key-scan Circuit connects the 4x6 key-matrix and reads the data of 24 keys

maximum as shown in Fig1. Furthermore, it operates correctly against the multiple key inputs.

(Conditional)

Fig. 1 Key-scan Matrix

S3

S0

S1

S2

K4 K3

K0

K1

K2

K5

NJU6010

KEY

ON

OFF

SW