MPC8377ECVRALDA datasheet(43/124 Pages) FREESCALE

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MPC8377E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

Enhanced Secure Digital Host Controller (eSDHC)

Due to the special implementation of the eSDHC, there are constraints regarding the clock and data signals

propagation delay on the user board. The constraints are for minimum and maximum delays, as well as

skew between the CLK and DAT/CMD signals.

In full speed mode, there is no need to add special delay on the data or clock signals. The user should make

sure to meet the timing requirements as described further within this document.

If the system is designed to support both high-speed and full-speed cards, the high-speed constraints

should be fulfilled. If the systems is designed to operate up to 25 MHz only, full-speed mode is

recommended.

11.1

eSDHC DC Electrical Characteristics

Table 40 provides the DC electrical characteristics for the eSDHC (SD/MMC) interface of the device.

11.2

eSDHC AC Timing Specifications (Full-Speed Mode)

This section describes the AC electrical specifications for the eSDHC (SD/MMC) interface of the device.

Table 41 provides the eSDHC AC timing specifications for full-speed mode as defined in Figure 27 and

Figure 28.

Table 40. eSDHC interface DC Electrical Characteristics

Parameter

Symbol

Condition

Min

Max

Unit

Input high voltage

VIH

—

0.625

× OVDD

OVDD +0.3

Input low voltage

VIL

—

–0.3

0.25

× OVDD

Input current

IIN

——

±30

μA

Output high voltage

VOH

IOH = –100 uA,

at OVDD(min)

0.75

× OVDD

—V

Output low voltage

VOL

IOL = +100 uA,

at OVDD(min)

—

0.125

× OVDD

Table 41. eSDHC AC Timing Specifications for Full-Speed Mode

At recommended operating conditions OVDD = 3.3 V ± 165 mV.

Parameter

Symbol 1

Min

Max

Unit

Notes

SD_CLK clock frequency—full speed mode

fSFSCK

025

MHz

—

SD_CLK clock cycle

tSFSCK

—

SD_CLK clock frequency—identification mode

fSIDCK

0400

KHz

—

SD_CLK clock low time

tSFSCKL

—

SD_CLK clock high time

tSFSCKH

—

SD_CLK clock rise and fall times

tSFSCKR/

tSFSCKF

—5

Input setup times: SD_CMD, SD_DATx, SD_CD to

SD_CLK

tSFSIVKH

5—

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