AT89LP4052 datasheet(24/94 Pages) ATMEL

24 / 94 page

3547J–MICRO–10/09

AT89LP2052/LP4052

16. Enhanced Timer/Counters

The AT89LP2052/LP4052 has two 16-bit Timer/Counter registers: Timer 0 and Timer 1. As a

Timer, the register is incremented every clock cycle. Thus, the register counts clock cycles.

Since a clock cycle consists of one oscillator period, the count rate is equal to the oscillator

frequency.

As a Counter, the register is incremented in response to a 1-to-0 transition at its corresponding

input pin, T0 or T1. The external input is sampled every clock cycle. When the samples show a

high in one cycle and a low in the next cycle, the count is incremented. The new count value

appears in the register during the cycle following the one in which the transition was detected.

Since 2 clock cycles are required to recognize a 1-to-0 transition, the maximum count rate is 1/2

of the oscillator frequency. There are no restrictions on the duty cycle of the input signal, but it

should be held for at least one full clock cycle to ensure that a given level is sampled at least

once before it changes.

Furthermore, the Timer or Counter functions for Timer 0 and Timer 1 have four operating modes:

variable width timer/counter, 16 bit auto-reload timer/counter, 8 bit auto-reload timer/counter,

and split timer/counter. The control bits C/T in the Special Function Register TMOD select the

Timer or Counter function. The bit pairs (M1, M0) in TMOD select the operating modes.

16.1

Mode 0

Both Timers in Mode 0 are 8-bit Counters with a variable prescaler. The prescaler may vary from

1 to 8 bits depending on the PSC bits in TCONB, giving the timer a range of 9 to 16 bits.

By default the timer is configured as a 13-bit timer compatible to Mode 0 in the standard 8051.

Figure 16-1 shows the Mode 0 operation as it applies to Timer 1 in 13-bit mode. As the count

rolls over from all “1”s to all “0”s, it sets the Timer interrupt flag TF1. The counted input is

enabled to the Timer when TR1 = 1 and either GATE = 0 or INT1 = 1. Setting GATE = 1 allows

the Timer to be controlled by external input INT1, to facilitate pulse width measurements. TR1 is

Table 15-4.

Port Pin Alternate Functions

Port

Configuration Bits

Alternate

Function

Notes

PxM0.y

PxM1.y

P1.0

P1M0.0

P1M1.0

AIN0

Input-only

P1.1

P1M0.1

P1M1.1

AIN1

Input-only

P1.4

P1M0.4

P1M1.4

Refer to Section 19.4 “SPI Pin

Configuration” on page 48

P1.5

P1M0.5

P1M1.5

MOSI

P1.6

P1M0.6

P1M1.6

MISO

P1.7

P1M0.7

P1M1.7

SCK

P3.0

P3M0.0

P3M1.0

RXD

P3.1

P3M0.1

P3M1.1

TXD

P3.2

P3M0.2

P3M1.2

INT0

P3.3

P3M0.3

P3M1.3

INT1

P3.4

P3M0.4

P3M1.4

Refer to Section 16.6 “Timer/Counter Pin

Configuration” on page 30

P3.5

P3M0.5

P3M1.5

P3.6

Not configurable

CMPOUT

Pin is tied to comparator output

AT89LP4052 Datasheet(PDF) 24 Page - ATMEL Corporation

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