AT89LP4052 datasheet(60/94 Pages) ATMEL

60 / 94 page

3547J–MICRO–10/09

AT89LP2052/LP4052

Figure 23-2. Flash Parallel Programming Device Connections

Note:

Sampling of pin P3.1 (RDY/BSY) is optional. During Parallel Programming, P3.1 will be pulled low

while the device is busy. Note that it does not require an external passive pull-up to VCC.

While CS is high, the interface is reset to its default state and P1 is tri-stated. CS should be

brought low before the first byte of a command is issued, and should return high only after the

last byte of the command has been strobed. Figure 23-3 shows a generic parallel write com-

mand sequence. Command, address, and data bytes are sampled from P1 on the rising edge of

the XTAL1 pulse. Figure 23-4 shows a generic parallel read command sequence. Command

and address bytes are sampled from P1 on the rising edge of the XTAL1 pulse. At the falling

edge of the fourth XTAL1 pulse the device enables P1 to output data. The data remains on P1

until CS is brought high. During reads the parallel programmer should tri-state P1 before the

negative edge of the fourth XTAL1 pulse to avoid bus contention.

Figure 23-3. Parallel Write Command Sequence

Figure 23-4. Parallel Read Command Sequence

AT89LP2052/LP4052

VCC

RST

P3.1

X TAL 1

P3.2

GND

2.7 to 5.5V

R DY/BSY

VPP

DATA

AAh

OPCODE

ADDRH

ADDRL

DATAIN

XTAL1

AAh

OPCODE

ADDRH

ADDRL

DATAOUT

XTAL1

AT89LP4052 Datasheet(PDF) 60 Page - ATMEL Corporation