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5242B–SEEPR–01/09

AT34C02C

The device address word consists of a mandatory one-zero sequence for the first four most-sig-

nificant bits (1010) for normal read and write operations and 0110 for writing to the write protect

register.

The next 3 bits are the A2, A1 and A0 device address bits for the AT34C02C EEPROM. These 3

bits must compare to their corresponding hard-wired input pins.

The eighth bit of the device address is the read/write operation select bit. A read operation is ini-

tiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is not

made, the chip will return to a standby state. The device will not acknowledge if the write protect

register has been programmed and the control code is 0110.

Write

Operations

BYTE WRITE: A write operation requires an 8-bit data word address following the device

address word and acknowledgment. Upon receipt of this address, the EEPROM will again

respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data

word, the EEPROM will output a zero and the addressing device, such as a microcontroller,

must terminate the write sequence with a stop condition. At this time the EEPROM enters an

internally-timed write cycle, t

write cycle and the EEPROM will not respond until the write is complete (see Figure 11 on page

12).

The device will acknowledge a write command, but not write the data, if the software or hard-

ware write protection has been enabled. The write cycle time must be observed even when the

write protection is enabled.

PAGE WRITE: The 2K device is capable of 16-byte page write.

A page write is initiated the same as a byte write, but the microcontroller does not send a stop

condition after the first data word is clocked in. Instead, after the EEPROM acknowledges

receipt of the first data word, the microcontroller can transmit up to fifteen more data words. The

EEPROM will respond with a zero after each data word received. The microcontroller must ter-

minate the page write sequence with a stop condition (see Figure 12 on page 12).

The data word address lower four bits are internally incremented following the receipt of each

data word. The higher data word address bits are not incremented, retaining the memory page

row location. When the word address, internally generated, reaches the page boundary, the fol-

lowing byte is placed at the beginning of the same page. If more than sixteen data words are

transmitted to the EEPROM, the data word address will “roll over” and previous data will be

overwritten. The address “roll over” during write is from the last byte of the current page to the

first byte of the same page.

The device will acknowledge a write command, but not write the data, if the software or hard-

ware write protection has been enabled. The write cycle time must be observed even when the

write protection is enabled.

ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the

EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a

start condition followed by the device address word. The read/write bit is representative of the

operation desired. Only if the internal write cycle has completed will the EEPROM respond with

a zero allowing the read or write sequence to continue.

7FH) while the hardware write protection, via the WP pin, is used to protect the entire array.