ATmega16U4 datasheet(143/408 Pages) ATMEL

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7766D–AVR–01/09

ATmega16U4/ATmega32U4

15.3

Counter Unit

The main part of the Timer/Counter4 is the programmable bi-directional counter unit. Figure 15-

3 shows a block diagram of the counter and its surroundings.

Figure 15-3. Counter Unit Block Diagram

Signal description (internal signals):

count

TCNT4 increment or decrement enable.

direction

Select between increment and decrement.

clear

Clear TCNT4 (set all bits to zero).

clk

Timer/Counter clock, referred to as clk

T4 in the following.

top

Signalize that TCNT4 has reached maximum value.

bottom

Signalize that TCNT4 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk

T4). The timer clock is generated from an synchronous system clock or an

asynchronous PLL clock using the Clock Select bits (CS4<3:0>) and the PLL Postscaler for High

Speed Timer bits (PLLTM1:0). When no clock source is selected (CS4<3:0> = 0) the timer is

stopped. However, the TCNT4 value can be accessed by the CPU, regardless of whether clk

is present or not. A CPU write overrides (has priority over) all counter clear or count operations.

The counting sequence of the Timer/Counter4 is determined by the setting of the WGM10 and

PWM4x bits located in the Timer/Counter4 Control Registers (TCCR4A, TCCR4C and

TCCR4D). For more details about advanced counting sequences and waveform generation, see

“Modes of Operation” on page 150. The Timer/Counter Overflow Flag (TOV4) is set according to

the mode of operation selected by the PWM4x and WGM40 bits. The Overflow Flag can be used

for generating a CPU interrupt.

15.3.1

Counter Initialization for Asynchronous Mode

To change Timer/Counter4 to the asynchronous mode follow the procedure below:

1. Enable PLL.

2. Wait 100µs for PLL to stabilize .

3. Poll the PLOCK bit until it is set.

4. Configure the PLLTM1:0 bits in the PLLFRQ register to enable the asynchronous mode

(different from 0:0 value).

DATA BUS

TCNT4

Control Logic

count

TOV4

top

Timer/Counter4 Count Enable

( From Prescaler )

bottom

direction

clear

PCK

PLLTM1:0

clk

ATmega16U4 Datasheet(PDF) 143 Page - ATMEL Corporation

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