ATmega16U4 datasheet(205/408 Pages) ATMEL

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7766D–AVR–01/09

ATmega16U4/ATmega32U4

18.9.1

Receiver Flow Control

The reception flow can be controlled by hardware using the RTS pin. The aim of the flow control

is to inform the external transmitter when the internal receive Fifo is full. Thus the transmitter can

stop sending characters. RTS usage and so associated flow control is enabled using RTSEN bit

in UCSRnD.

Figure 5. shows a reception example.

Figure 5. Reception Flow Control Waveform Example

Figure 6. RTS behavior

RTS will rise at 2/3 of the last received stop bit if the receive fifo is full.

To ensure reliable transmissions, even after a RTS rise, an extra-data can still be received and

stored in the Receive Shift Register.

18.9.2

Transmission Flow Control

The transmission flow can be controlled by hardware using the CTS pin controlled by the exter-

nal receiver. The aim of the flow control is to stop transmission when the receiver is full of data

(CTS = 1). CTS usage and so associated flow control is enabled using CTSEN bit in UCSRnD.

The CTS pin is sampled at each CPU write and at the middle of the last stop bit that is cur-

rently being sent.

Figure 7. CTS behavior

RTS

RXD

C1 C2

FIFO

CPU Read

Index

RTS

RXD

Start

Byte0

Stop

Start

Byte1

Stop

Read from CPU

Start

Byte2

1 additional byte may be sent

if the transmitter misses the RTS trig

CTS

TXD

Start

Byte0

Stop

Start

Byte1

Stop

Start

Byte2

sample

Write from CPU

sample

ATmega16U4 Datasheet(PDF) 205 Page - ATMEL Corporation

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