ATmega16U4 datasheet(298/408 Pages) ATMEL

298 / 408 page

298

7766D–AVR–01/09

ATmega16U4/ATmega32U4

Figure 24-6. ADC Timing Diagram, Auto Triggered Conversion

Figure 24-7. ADC Timing Diagram, Free Running Conversion

24.4.1

Differential Channels

When using differential channels, certain aspects of the conversion need to be taken into

consideration.

Differential conversions are synchronized to the internal clock CK

ADC2 equal to half the ADC

clock frequency. This synchronization is done automatically by the ADC interface in such a way

that the sample-and-hold occurs at a specific phase of CK

ADC2. A conversion initiated by the

user (i.e., all single conversions, and the first free running conversion) when CK

ADC2 is low will

take the same amount of time as a single ended conversion (13 ADC clock cycles from the next

prescaled clock cycle). A conversion initiated by the user when CK

ADC2 is high will take 14 ADC

Table 24-1.

ADC Conversion Time

Condition

First

Conversion

Normal

Conversion,

Single Ended

Auto Triggered

Convertion

Sample & Hold

(Cycles from Start of Convention)

14.5

1.5

Conversion Time

(Cycles)

13.5

Sign and MSB of Result

LSB of Result

ADC Clock

Trigger

Source

ADIF

ADCH

ADCL

Cycle Number

One Conversion

Next Conversion

Conversion

Complete

Prescaler

Reset

ADATE

Prescaler

Reset

Sample &

Hold

MUX and REFS

Update

Sign and MSB of Result

LSB of Result

ADC Clock

ADSC

ADIF

ADCH

ADCL

Cycle Number

One Conversion

Next Conversion

Conversion

Complete

Sample & Hold

MUX and REFS

Update

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