ATmega328P datasheet(164/345 Pages) ATMEL

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164

7810A–AVR–11/09

ATmega328P [Preliminary]

Figure 18-3. SPI Transfer Format with CPHA = 0

Figure 18-4. SPI Transfer Format with CPHA = 1

18.5

18.5.1

SPCR – SPI Control Register

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if

the Global Interrupt Enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI

operations.

Bit 1

Bit 6

LSB

MSB

SCK (CPOL = 0)

mode 0

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 2

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

MSB first (DORD = 0)

LSB first (DORD = 1)

SCK (CPOL = 0)

mode 1

SAMPLE I

MOSI/MISO

CHANGE 0

MOSI PIN

CHANGE 0

MISO PIN

SCK (CPOL = 1)

mode 3

MSB

LSB

Bit 6

Bit 1

Bit 5

Bit 2

Bit 4

Bit 3

Bit 4

Bit 2

Bit 5

Bit 1

Bit 6

LSB

MSB

MSB first (DORD = 0)

LSB first (DORD = 1)

Bit

0x2C (0x4C)

SPIE

SPE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

SPCR

Read/Write

R/W

Initial Value

ATmega328P Datasheet(PDF) 164 Page - ATMEL Corporation

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