ATmega328P datasheet(165/345 Pages) ATMEL

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165

7810A–AVR–11/09

ATmega328P [Preliminary]

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic

zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,

and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-

ter mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low

when idle. Refer to Figure 18-3 and Figure 18-4 for an example. The CPOL functionality is sum-

marized below:

• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or

trailing (last) edge of SCK. Refer to Figure 18-3 and Figure 18-4 for an example. The CPOL

functionality is summarized below:

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have

no effect on the Slave.

The relationship between SCK and the Oscillator Clock frequency f

osc is shown in the following

table:

Table 18-3.

CPOL Functionality

CPOL

Leading Edge

Trailing Edge

Rising

Falling

Rising

Table 18-4.

CPHA Functionality

CPHA

Leading Edge

Trailing Edge

Sample

Setup

Sample

Table 18-5.

Relationship Between SCK and the Oscillator Frequency

SPI2X

SPR1

SPR0

SCK Frequency

osc/4

osc/16

osc/64

osc/128

osc/2

osc/8

osc/32

osc/64

ATmega328P Datasheet(PDF) 165 Page - ATMEL Corporation

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