ATmega328P datasheet(166/345 Pages) ATMEL

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166

7810A–AVR–11/09

ATmega328P [Preliminary]

18.5.2

SPSR – SPI Status Register

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in

SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is

in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the

SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The

WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,

and then accessing the SPI Data Register.

• Bit 5..1 – Res: Reserved Bits

These bits are reserved bits in the ATmega328P and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI

is in Master mode (see Table 18-5). This means that the minimum SCK period will be two CPU

clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f

osc/4

or lower.

The SPI interface on the ATmega328P is also used for program memory and EEPROM down-

loading or uploading. See page 299 for serial programming and verification.

18.5.3

SPDR – SPI Data Register

The SPI Data Register is a read/write register used for data transfer between the Register File

and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis-

ter causes the Shift Register Receive buffer to be read.

Bit

0x2D (0x4D)

SPIF

WCOL

–

SPI2X

SPSR

Read/Write

R/W

Initial Value

Bit

765

43210

0x2E (0x4E)

MSB

LSB

SPDR

Read/Write

R/W

Initial Value

XXXXXXX

Undefined

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