210

8021E–AVR–07/09

ATmega329P/3290P

When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.

21. Analog to Digital Converter

21.1

Features

21.2

Overview

The ATmega329P/3290P features a 10-bit successive approximation ADC. The ADC is con-

nected to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs

constructed from the pins of Port F. The single-ended voltage inputs refer to 0V (GND).

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is

held at a constant level during conversion. A block diagram of the ADC is shown in Figure 21-1.

The ADC has a separate analog supply voltage pin, AVCC. AV

0.3V from V

pin.

Internal reference voltages of nominally 1.1V or AVCC are provided On-chip. The voltage refer-

ence may be externally decoupled at the AREF pin by a capacitor for better noise performance.

The PRADC, in ”PRR – Power Reduction Register” on page 42 must be written to zero to enable

the ADC module.