| Electronic Components Datasheet Search |
|
ATmega3290P Datasheet(PDF) 42 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
ATmega3290P Datasheet(HTML) 42 Page - ATMEL Corporation |
|
42 / 385 page ![]() 42 8021E–AVR–07/09 ATmega329P/3290P The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles. • Bit 5 – BODSE: BOD Sleep Enable BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence. 9.10.3 PRR – Power Reduction Register • Bits 7, 6, 5 - Res: Reserved bits These bits are reserved bits in ATmega329P/3290P and will always read as zero. • Bit 4 - PRLCD: Power Reduction LCD Writing logic one to this bit shuts down the LCD controller. The LCD controller must be disabled and the display discharged before shut down. See "Disabling the LCD" on page 217 for details on how to disable the LCD controller. • Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing logic one to this bit shuts down the Timer/Counter1 module. When Timer/Counter1 is enabled, operation will continue like before the shutdown. • Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface Writing logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re-initialized to ensure proper operation. • Bit 1 - PRUSART: Power Reduction USART Writing logic one to this bit shuts down the USART by stopping the clock to the module. When waking up the USART again, the USART should be re-initialized to ensure proper operation. • Bit 0 - PRADC: Power Reduction ADC Writing logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. Note: The Analog Comparator is disabled using the ACD-bit in the ”ACSR – Analog Comparator Control and Status Register” on page 208. Bit 765 4 3 2 1 0 (0x64) – – – PRLCD PRTIM1 PRSPI PRUSART0 PRADC PRR Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |