ATmega3290P datasheet(50/385 Pages) ATMEL

50 / 385 page

8021E–AVR–07/09

ATmega329P/3290P

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written

to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit

has logic level one. To disable an enabled Watchdog Timer, the following procedure must be

followed:

In the same operation, write a logic one to WDCE and WDE. A logic one must be written

to WDE even though it is set to one before the disable operation starts.

Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm

described above. ”Timed Sequences for Changing the Configuration of the Watchdog Timer” on

page 48.

• Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-

dog Timer is enabled. The different prescaling values and their corresponding Time-out Periods

are shown in Table 10-2 on page 50.

Table 10-2.

Watchdog Timer Prescale Select

WDP2

WDP1

WDP0

Number of WDT

Oscillator Cycles

Typical Time-out at

VCC = 3.0V

Typical Time-out at

VCC = 5.0V

16K cycles

17.1 ms

16.3 ms

32K cycles

34.3 ms

32.5 ms

64K cycles

68.5 ms

65 ms

128K cycles

0.14 s

0.13 s

256K cycles

0.27 s

0.26 s

512K cycles

0.55 s

0.52 s

1,024K cycles

1.1 s

1.0 s

2,048K cycles

2.2 s

2.1 s

ATmega3290P Datasheet(PDF) 50 Page - ATMEL Corporation

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