ATmega16A datasheet(277/352 Pages) ATMEL

277 / 352 page

277

8154B–AVR–07/09

ATmega16A

26.8.2

SPI Serial Programming Algorithm

When writing serial data to the ATmega16A, data is clocked on the rising edge of SCK.

When reading data from the ATmega16A, data is clocked on the falling edge of SCK. See Figure

27-5 for timing details.

To program and verify the ATmega16A in the SPI Serial Programming mode, the following

sequence is recommended (See four byte instruction formats in Figure 26-13 on page 278

Power-up sequence:

Apply power between V

CC and GND while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse of at least two CPU clock cycles duration

after SCK has been set to “0”.

Wait for at least 20 ms and enable SPI Serial Programming by sending the Program-

ming Enable serial instruction to pin MOSI.

The SPI Serial Programming instructions will not work if the communication is out of

synchronization. When in sync. the second byte ($53), will echo back when issuing the

third byte of the Programming Enable instruction. Whether the echo is correct or not, all

four bytes of the instruction must be transmitted. If the $53 did not echo back, give

RESET a positive pulse and issue a new Programming Enable command.

The Flash is programmed one page at a time. The page size is found in Table 26-5 on page

267

. The memory page is loaded one byte at a time by supplying the 6 LSB of the

address and data together with the Load Program Memory Page instruction. To ensure

correct loading of the page, the data Low byte must be loaded before data High byte is

applied for a given address. The Program Memory Page is stored by loading the Write

Program Memory Page instruction with the 7 MSB of the address. If polling is not used,

the user must wait at least t

WD_FLASH before issuing the next page. (See Table 26-12).

Accessing the SPI Serial Programming interface before the Flash write operation com-

pletes can result in incorrect programming.

The EEPROM array is programmed one byte at a time by supplying the address and

data together with the appropriate Write instruction. An EEPROM memory location is

first automatically erased before new data is written. If polling is not used, the user must

wait at least t

WD_EEPROM before issuing the next byte. (See Table 26-12). In a chip

erased device, no $FFs in the data file(s) need to be programmed.

Any memory location can be verified by using the Read instruction which returns the

content at the selected address at serial output MISO.

At the end of the programming session, RESET can be set high to commence normal

operation.

Power-off sequence (if needed):

Set RESET to “1”.

Turn V

CC power off.

26.8.3

Data Polling Flash

When a page is being programmed into the Flash, reading an address location within the page

being programmed will give the value $FF. At the time the device is ready for a new page, the

programmed value will read correctly. This is used to determine when the next page can be writ-

ten. Note that the entire page is written simultaneously and any address within the page can be

used for polling. Data polling of the Flash will not work for the value $FF, so when programming

this value, the user will have to wait for at least t

WD_FLASH before programming the next page. As

a chip erased device contains $FF in all locations, programming of addresses that are meant to

contain $FF, can be skipped. See Table 26-12 for t

WD_FLASH value

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