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ATmega32A Datasheet(PDF) 138 Page - ATMEL Corporation |
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ATmega32A Datasheet(HTML) 138 Page - ATMEL Corporation |
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138 / 352 page ![]() 138 8155B–AVR–07/09 ATmega32A 18. SPI – Serial Peripheral Interface 18.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode 18.2 Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega32A and peripheral devices or between several AVR devices. Figure 18-1. SPI Block Diagram (1) Note: 1. Refer to Figure 1-1 on page 2, and Table 12-6 on page 59 for SPI pin placement. The interconnection between Master and Slave CPUs with SPI is shown in Figure 18-2. The sys- tem consists of two Shift Registers, and a Master clock generator. The SPI Master initiates the DIVIDER /2/4/8/16/32/64/128 |
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