ATmega32A datasheet(136/352 Pages) ATMEL

136 / 352 page

136

8155B–AVR–07/09

ATmega32A

The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2,

the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary stor-

age register is read.

17.11.5

TIMSK – Timer/Counter Interrupt Mask Register

• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable

When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if

a compare match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the Timer/Counter

Interrupt Flag Register – TIFR.

• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable

When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the

Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter Interrupt

Flag Register – TIFR.

17.11.6

TIFR – Timer/Counter Interrupt Flag Register

• Bit 7 – OCF2: Output Compare Flag 2

The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the

data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the

corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare match Interrupt Enable), and

OCF2 are set (one), the Timer/Counter2 Compare match Interrupt is executed.

• Bit 6 – TOV2: Timer/Counter2 Overflow Flag

The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared

by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Inter-

rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In

PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00.

Bit

210

OCIE2

TOIE2

TICIE1

OCIE1A

OCIE1B

TOIE1

OCIE0

TOIE0

TIMSK

Read/Write

R/W

Initial Value

Bit

765

432

OCF2

TOV2

ICF1

OCF1A

OCF1B

TOV1

OCF0

TOV0

TIFR

Read/Write

R/W

Initial Value

ATmega32A Datasheet(PDF) 136 Page - ATMEL Corporation

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