ATmega32A datasheet(134/352 Pages) ATMEL

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134

8155B–AVR–07/09

ATmega32A

Table 17-4 shows the COM2[1:0] bit functionality when the WGM21:0 bits are set to fast PWM

mode.

Note:

1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare

match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 125 for

more details.

Table 17-5 shows the COM2[1:0] bit functionality when the WGM21:0 bits are set to phase cor-

rect PWM mode

Note:

1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare

match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page

127 for more details.

• Bit 2:0 – CS2[2:0]: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table

17-6.

Table 17-4.

Compare Output Mode, Fast PWM Mode(1)

COM21

COM20

Description

Normal port operation, OC2 disconnected.

Reserved

Clear OC2 on compare match, set OC2 at BOTTOM,

(non-inverting mode)

Set OC2 on compare match, clear OC2 at BOTTOM,

(inverting mode)

Table 17-5.

Compare Output Mode, Phase Correct PWM Mode

(1)

COM21

COM20

Description

Normal port operation, OC2 disconnected.

Reserved

Clear OC2 on compare match when up-counting. Set OC2 on compare match

when downcounting.

Set OC2 on compare match when up-counting. Clear OC2 on compare match

when downcounting.

Table 17-6.

Clock Select Bit Description

CS22

CS21

CS20

Description

No clock source (Timer/Counter stopped).

clk

T2S/(No prescaling)

clk

T2S/8 (From prescaler)

clk

T2S/32 (From prescaler)

clk

T2S/64 (From prescaler)

clk

T2S/128 (From prescaler)

clkT2S/256 (From prescaler)

clkT2S/1024 (From prescaler)

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