ATmega644PA datasheet(263/468 Pages) ATMEL

263 / 468 page

263

8152G–AVR–11/09

ATmega164PA/324PA/644PA/1284P

• TCK: Test Clock. JTAG operation is synchronous to TCK.

• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register

(Scan Chains).

• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.

The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not

provided.

When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins, and the

TAP controller is in reset. When programmed, the input TAP signals are internally pulled high

and the JTAG is enabled for Boundary-scan and programming. The device is shipped with this

fuse programmed.

For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni-

tored by the debugger to be able to detect external reset sources. The debugger can also pull

the RESET pin low to reset the whole system, assuming only open collectors on the reset line

are used in the application.

Figure 23-1. Block Diagram

TAP

CONTROLLER

TDI

TDO

TCK

TMS

FLASH

MEMORY

AVR CPU

DIGITAL

PERIPHERAL

UNITS

JTAG / AVR CORE

COMMUNICATION

INTERFACE

BREAKPOINT

UNIT

FLOW CONTROL

UNIT

OCD STATUS

AND CONTROL

INTERNAL

SCAN

CHAIN

INSTRUCTION

BYPASS

JTAG PROGRAMMING

INTERFACE

Instruction

Address

Data

BREAKPOINT

SCAN CHAIN

ADDRESS

DECODER

ANALOG

PERIPHERIAL

UNITS

I/O PORT 0

I/O PORT n

BOUNDARY SCAN CHAIN

Analog inputs

Control & Clock lines

DEVICE BOUNDARY

ATmega644PA Datasheet(PDF) 263 Page - ATMEL Corporation

ATmega644PA Datasheet(HTML) 263 Page - ATMEL Corporation

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