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ATmega644PA Datasheet(PDF) 260 Page - ATMEL Corporation |
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ATmega644PA Datasheet(HTML) 260 Page - ATMEL Corporation |
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260 / 468 page  260 8152G–AVR–11/09 ATmega164PA/324PA/644PA/1284P 22.9.3 ADCL and ADCH – The ADC Data Register ADLAR = 0 ADLAR = 1 When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in ”ADC Conversion Result” on page 255. 22.9.4 ADCSRB – ADC Control and Status Register B 10 0 16 10 1 32 11 0 64 11 1 128 Table 22-5. ADC Prescaler Selections (Continued) ADPS2 ADPS1 ADPS0 Division Factor Bit 15 14131211 10 9 8 (0x79) –––––– ADC9 ADC8 ADCH (0x78) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 765432 10 Read/Write RRRR RRRR RRRR RRRR Initial Value 000000 00 000000 00 Bit 15 14131211 10 9 8 (0x79) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH (0x78) ADC1 ADC0 –––– –– ADCL 765432 10 Read/Write RRRR RRRR RRRR RRRR Initial Value 000000 00 000000 00 Bit 7 65 4 3 21 0 (0x7B) – ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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