33879 datasheet(10/23 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

33879

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 5. Dynamic Electrical Characteristics

Characteristics noted under conditions 3.1 V

≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted.

Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25°C.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING

Output Slew Rate Low Side Configuration(11)

RLOAD = 620Ω, CL = 200pF

tSR(RISE)

0.1

0.5

1.0

μs

Output Slew Rate Low Side Configuration(11)

RLOAD = 620 Ω, CL = 200 pF

tSR(FALL)

0.1

0.5

1.0

μs

Output Rise Time High Side Configuration(11)

RLOAD = 620 Ω, CL = 200 pF

tSR(RISE)

0.1

0.3

1.0

μs

Output Fall Time High Side Configuration(11)

RLOAD = 620 Ω, CL = 200 pF

tSR(FALL)

0.1

0.3

1.0

μs

Output Turn ON Delay Time, High Side and Low Side Configuration(12)

tDLY(ON)

1.0

μs

Output Turn OFF Delay Time, High Side and Low Side Configuration(12)

tDLY(OFF)

1.0

100

μs

Output Fault Delay Time(13)

tFAULT

100

–

300

μs

Power-ON Reset Delay

Delay Time Required from Rising Edge of EN and VDD to SPI Active

tPOR

100

–

μs

Low-State Duration on VDD or EN for Reset

VDD or EN ≤ 0.2 V

tRESET

100

–

µs

Notes

11.

Output slew rate respectively measured across a 620

Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points.

CL capacitor is connected from Drain or Source output to Ground.

12.

Output turn ON and OFF delay time measured from 50 percent rising edge of CS to the beginning of the 10 and 90 percent transition

points.

13.

Duration of fault before fault bit is set. Duration between access times must be greater than 300

μs to read faults.

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