DS1977

21 of 29

Figure 11. READ/WRITE TIMING DIAGRAM (continued)

Write-Zero Time Slot

RESISTOR

MASTER

0V



Read-Data Time Slot

RESISTOR

MASTER

DS1977

0V

Master

Sampling

Window



SLAVE-TO-MASTER

data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again.

When responding with a 1, the DS1977 will not hold the data line low at all, and the voltage starts rising as soon as

IMPROVED NETWORK BEHAVIOR

1-Wire networks can only be terminated during transients controlled by the bus master (1-Wire driver) and are

therefore susceptible to noise of various origins. Depending on the physical size and topology of the network,

reflections from end points and branch points can add up or cancel each other to some extent. Such reflections are

visible as glitches or ringing on the 1-Wire communication line. A glitch during the rising edge of a time slot can

cause a slave device to lose synchronization with the master and, as a consequence, result in a search ROM

command coming to a dead end. For better performance in network applications, the DS1977 uses a new 1-Wire

front end, which makes it less sensitive to noise and also reduces the magnitude of noise injected by the slave

device itself.

The 1-Wire front end of the DS1977 differs from traditional slave devices in four characteristics.

1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line

impedance than a digitally switched transistor, converting the high frequency ringing known from traditional